RAJA
RAJA provides a collection of platform portability abstractions for C++ HPC applications.
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TensorRegister.hpp File Reference

RAJA header file defining SIMD/SIMT register operations. More...

#include "RAJA/config.hpp"
#include "RAJA/util/macros.hpp"
#include "camp/camp.hpp"
#include "RAJA/pattern/tensor/TensorLayout.hpp"
#include "RAJA/pattern/tensor/internal/TensorRef.hpp"
#include "RAJA/pattern/tensor/internal/TensorRegisterBase.hpp"
#include "RAJA/policy/tensor/arch.hpp"

Go to the source code of this file.

Namespaces

 RAJA
 
 RAJA::internal
 
 RAJA::internal::expt
 
 RAJA::expt
 

Functions

template<typename LEFT , typename RIGHT , typename std::enable_if< std::is_arithmetic< LEFT >::value, bool >::type = true, typename std::enable_if< std::is_base_of< RAJA::internal::expt::TensorRegisterConcreteBase, RIGHT >::value, bool >::type = true>
RAJA_INLINE RAJA_HOST_DEVICE RIGHT RAJA::expt::operator+ (LEFT const &lhs, RIGHT const &rhs)
 
template<typename LEFT , typename RIGHT , typename std::enable_if< std::is_arithmetic< LEFT >::value, bool >::type = true, typename std::enable_if< std::is_base_of< RAJA::internal::expt::TensorRegisterConcreteBase, RIGHT >::value, bool >::type = true>
RAJA_INLINE RAJA_HOST_DEVICE RIGHT RAJA::expt::operator- (LEFT const &lhs, RIGHT const &rhs)
 
template<typename LEFT , typename RIGHT , typename std::enable_if< std::is_arithmetic< LEFT >::value, bool >::type = true, typename std::enable_if< std::is_base_of< RAJA::internal::expt::TensorRegisterConcreteBase, RIGHT >::value, bool >::type = true>
RAJA_INLINE RAJA_HOST_DEVICE RIGHT RAJA::expt::operator* (LEFT const &lhs, RIGHT const &rhs)
 
template<typename LEFT , typename RIGHT , typename std::enable_if< std::is_arithmetic< LEFT >::value, bool >::type = true, typename std::enable_if< std::is_base_of< RAJA::internal::expt::TensorRegisterConcreteBase, RIGHT >::value, bool >::type = true>
RAJA_INLINE RAJA_HOST_DEVICE RIGHT RAJA::expt::operator/ (LEFT const &lhs, RIGHT const &rhs)
 

Detailed Description

RAJA header file defining SIMD/SIMT register operations.