20 #ifndef RAJA_pattern_tensor_VectorRegisterImpl_HPP
21 #define RAJA_pattern_tensor_VectorRegisterImpl_HPP
23 #include "RAJA/config.hpp"
27 #include "camp/camp.hpp"
41 template<
typename REGISTER_POLICY,
typename T, camp::
idx_t SIZE>
47 RAJA::expt::TensorRegister<REGISTER_POLICY,
49 RAJA::expt::VectorLayout,
61 camp::idx_seq<SIZE>>>;
66 static constexpr camp::idx_t s_num_elem = SIZE;
69 typename register_type::int_vector_type::element_type;
76 static constexpr camp::idx_t s_register_num_elem = register_type::s_num_elem;
78 static constexpr camp::idx_t s_num_full_registers =
79 s_num_elem / s_register_num_elem;
81 static constexpr camp::idx_t s_num_partial_lanes =
82 s_num_elem % s_register_num_elem;
84 static constexpr camp::idx_t s_num_registers = (s_num_partial_lanes > 0)
85 ? s_num_full_registers + 1
86 : s_num_full_registers;
90 static constexpr camp::idx_t s_shift_per_register = log_base2_t::value;
92 static constexpr camp::idx_t s_mask_per_register =
93 (1 << log_base2_t::value) - 1;
96 static constexpr camp::idx_t s_final_register = s_num_partial_lanes == 0
97 ? s_num_full_registers - 1
98 : s_num_full_registers;
100 template<
typename IDX>
101 RAJA_INLINE
RAJA_HOST_DEVICE constexpr
static auto to_register(IDX i) -> IDX
103 return i >> IDX(s_shift_per_register);
106 template<
typename IDX>
109 return i & IDX(s_mask_per_register);
112 using base_type::m_registers;
133 template<
typename RHS,
134 typename std::enable_if<
143 *
this = rhs.eval(base_type::s_get_default_tile());
146 template<
typename... REGS>
155 static constexpr
bool is_root() {
return register_type::is_root(); }
164 template<camp::
idx_t STRIDE_ONE_DIM>
167 return STRIDE_ONE_DIM == 0;
178 return dim == 0 ? s_num_elem : 0;
190 this->broadcast(value);
203 template<
typename T2,
typename L,
typename RP>
206 return y.left_vector_multiply(*
this);
210 template<
typename REF_TYPE>
213 template<
typename REF_TYPE>
216 RefBridge<REF_TYPE>::load_ref(*
this, ref);
220 template<
typename REF_TYPE>
223 RefBridge<REF_TYPE>::store_ref(*
this, ref);
227 template<
typename POINTER_TYPE,
230 camp::idx_t STRIDE_ONE_DIM>
232 RAJA::internal::expt::
233 TensorRef<POINTER_TYPE, INDEX_TYPE, TENSOR_SIZE, 1, STRIDE_ONE_DIM>>
237 TensorRef<POINTER_TYPE, INDEX_TYPE, TENSOR_SIZE, 1, STRIDE_ONE_DIM>;
251 if (STRIDE_ONE_DIM == 0)
256 #ifdef RAJA_ENABLE_VECTOR_STATS
257 RAJA::tensor_stats::num_vector_load_packed++;
259 self.load_packed(ptr);
264 #ifdef RAJA_ENABLE_VECTOR_STATS
265 RAJA::tensor_stats::num_vector_load_packed_n++;
276 #ifdef RAJA_ENABLE_VECTOR_STATS
277 RAJA::tensor_stats::num_vector_load_strided++;
279 self.load_strided(ptr, ref.
m_stride[0]);
284 #ifdef RAJA_ENABLE_VECTOR_STATS
285 RAJA::tensor_stats::num_vector_load_strided_n++;
304 if (STRIDE_ONE_DIM == 0)
309 #ifdef RAJA_ENABLE_VECTOR_STATS
310 RAJA::tensor_stats::num_vector_store_packed++;
312 self.store_packed(ptr);
317 #ifdef RAJA_ENABLE_VECTOR_STATS
318 RAJA::tensor_stats::num_vector_store_packed_n++;
329 #ifdef RAJA_ENABLE_VECTOR_STATS
330 RAJA::tensor_stats::num_vector_store_strided++;
332 self.store_strided(ptr, ref.
m_stride[0]);
337 #ifdef RAJA_ENABLE_VECTOR_STATS
338 RAJA::tensor_stats::num_vector_store_strided_n++;
346 template<
typename POINTER_TYPE,
349 INDEX_TYPE STRIDE_VALUE,
350 INDEX_TYPE BEGIN_VALUE,
351 INDEX_TYPE SIZE_VALUE,
352 camp::idx_t STRIDE_ONE_DIM>
357 camp::int_seq<INDEX_TYPE, STRIDE_VALUE>,
358 camp::int_seq<INDEX_TYPE, BEGIN_VALUE>,
359 camp::int_seq<INDEX_TYPE, SIZE_VALUE>,
367 camp::int_seq<INDEX_TYPE, STRIDE_VALUE>,
368 camp::int_seq<INDEX_TYPE, BEGIN_VALUE>,
369 camp::int_seq<INDEX_TYPE, SIZE_VALUE>,
381 auto ptr = ref.m_pointer + ref.m_tile.m_begin[0] * ref.m_stride[0];
384 if (STRIDE_ONE_DIM == 0)
389 #ifdef RAJA_ENABLE_VECTOR_STATS
390 RAJA::tensor_stats::num_vector_load_packed++;
392 self.load_packed(ptr);
397 #ifdef RAJA_ENABLE_VECTOR_STATS
398 RAJA::tensor_stats::num_vector_load_packed_n++;
400 self.load_packed_n(ptr, ref.m_tile.m_size[0]);
409 #ifdef RAJA_ENABLE_VECTOR_STATS
410 RAJA::tensor_stats::num_vector_load_strided++;
412 self.load_strided(ptr, ref.m_stride[0]);
417 #ifdef RAJA_ENABLE_VECTOR_STATS
418 RAJA::tensor_stats::num_vector_load_strided_n++;
420 self.load_strided_n(ptr, ref.m_stride[0], ref.m_tile.m_size[0]);
434 auto ptr = ref.m_pointer + ref.m_tile.m_begin[0] * ref.m_stride[0];
437 if (STRIDE_ONE_DIM == 0)
442 #ifdef RAJA_ENABLE_VECTOR_STATS
443 RAJA::tensor_stats::num_vector_store_packed++;
445 self.store_packed(ptr);
450 #ifdef RAJA_ENABLE_VECTOR_STATS
451 RAJA::tensor_stats::num_vector_store_packed_n++;
453 self.store_packed_n(ptr, ref.m_tile.m_size[0]);
462 #ifdef RAJA_ENABLE_VECTOR_STATS
463 RAJA::tensor_stats::num_vector_store_strided++;
465 self.store_strided(ptr, ref.m_stride[0]);
470 #ifdef RAJA_ENABLE_VECTOR_STATS
471 RAJA::tensor_stats::num_vector_store_strided_n++;
473 self.store_strided_n(ptr, ref.m_stride[0], ref.m_tile.m_size[0]);
487 for (camp::idx_t reg = 0; reg < s_num_full_registers; ++reg)
489 m_registers[reg].
load_packed(ptr + reg * s_register_num_elem);
491 if (s_num_partial_lanes)
494 ptr + s_final_register * s_register_num_elem, s_num_partial_lanes);
507 for (camp::idx_t reg = 0; reg < s_num_full_registers; ++reg)
509 m_registers[reg].
load_strided(ptr + reg * s_register_num_elem * stride,
512 if (s_num_partial_lanes)
515 ptr + s_final_register * s_register_num_elem * stride, stride,
516 s_num_partial_lanes);
529 for (camp::idx_t reg = 0; reg < s_num_full_registers; ++reg)
531 if (N >= reg * s_register_num_elem + s_register_num_elem)
533 m_registers[reg].
load_packed(ptr + reg * s_register_num_elem);
537 m_registers[reg].
load_packed_n(ptr + reg * s_register_num_elem,
538 N - reg * s_register_num_elem);
540 for (camp::idx_t r = reg + 1; r < s_num_full_registers; ++r)
542 m_registers[r].broadcast(0);
547 if (s_num_partial_lanes)
550 ptr + s_final_register * s_register_num_elem,
551 N - s_final_register * s_register_num_elem);
564 for (camp::idx_t reg = 0; reg < s_num_full_registers; ++reg)
566 if (N >= reg * s_register_num_elem + s_register_num_elem)
568 m_registers[reg].
load_strided(ptr + reg * s_register_num_elem * stride,
574 reg * s_register_num_elem * stride,
575 stride, N - reg * s_register_num_elem);
576 for (camp::idx_t r = reg + 1; r < s_num_full_registers; ++r)
578 m_registers[r].broadcast(0);
583 if (s_num_partial_lanes)
586 ptr + s_final_register * s_register_num_elem * stride, stride,
587 N - s_final_register * s_register_num_elem);
606 for (camp::idx_t reg = 0; reg < s_num_full_registers; ++reg)
608 m_registers[reg].
gather(ptr, offsets.vec(reg));
610 if (s_num_partial_lanes)
612 m_registers[s_final_register].
gather_n(ptr, offsets.vec(s_final_register),
613 s_num_partial_lanes);
632 for (camp::idx_t reg = 0; reg < s_num_full_registers; ++reg)
634 if (N >= reg * s_register_num_elem + s_register_num_elem)
636 m_registers[reg].
gather(ptr, offsets.vec(reg));
640 m_registers[reg].
gather_n(ptr, offsets.vec(reg),
641 N - reg * s_register_num_elem);
642 for (camp::idx_t r = reg + 1; r < s_num_full_registers; ++r)
644 m_registers[r].broadcast(0);
649 if (s_num_partial_lanes)
651 m_registers[s_final_register].
gather_n(ptr, offsets.vec(s_final_register),
652 N - s_final_register *
653 s_register_num_elem);
666 for (camp::idx_t reg = 0; reg < s_num_full_registers; ++reg)
668 m_registers[reg].
store_packed(ptr + reg * s_register_num_elem);
670 if (s_num_partial_lanes)
673 ptr + s_final_register * s_register_num_elem, s_num_partial_lanes);
686 for (camp::idx_t reg = 0; reg < s_num_full_registers; ++reg)
688 m_registers[reg].
store_strided(ptr + reg * s_register_num_elem * stride,
691 if (s_num_partial_lanes)
694 ptr + s_final_register * s_register_num_elem * stride, stride,
695 s_num_partial_lanes);
708 for (camp::idx_t reg = 0; reg < s_num_full_registers; ++reg)
710 if (N >= reg * s_register_num_elem + s_register_num_elem)
712 m_registers[reg].
store_packed(ptr + reg * s_register_num_elem);
717 N - reg * s_register_num_elem);
721 if (s_num_partial_lanes)
724 ptr + s_final_register * s_register_num_elem,
725 N - s_final_register * s_register_num_elem);
738 for (camp::idx_t reg = 0; reg < s_num_full_registers; ++reg)
740 if (N >= reg * s_register_num_elem + s_register_num_elem)
742 m_registers[reg].
store_strided(ptr + reg * s_register_num_elem * stride,
748 reg * s_register_num_elem * stride,
749 stride, N - reg * s_register_num_elem);
753 if (s_num_partial_lanes)
756 ptr + s_final_register * s_register_num_elem * stride, stride,
757 N - s_final_register * s_register_num_elem);
777 for (camp::idx_t reg = 0; reg < s_num_full_registers; ++reg)
779 m_registers[reg].
scatter(ptr, offsets.vec(reg));
781 if (s_num_partial_lanes)
784 ptr, offsets.vec(s_final_register), s_num_partial_lanes);
805 for (camp::idx_t reg = 0; reg < s_num_full_registers; ++reg)
807 if (N >= reg * s_register_num_elem + s_register_num_elem)
809 m_registers[reg].
scatter(ptr, offsets.vec(reg));
813 m_registers[reg].
scatter_n(ptr, offsets.vec(reg),
814 N - reg * s_register_num_elem);
819 if (s_num_partial_lanes)
822 ptr, offsets.vec(s_final_register),
823 N - s_num_full_registers * s_register_num_elem);
834 for (camp::idx_t reg = 0; reg < s_num_full_registers; ++reg)
836 result.vec(reg) = m_registers[reg].
divide(den.vec(reg));
838 if (s_num_partial_lanes)
840 result.vec(s_final_register) = m_registers[s_final_register].
divide_n(
841 den.vec(s_final_register), s_num_partial_lanes);
859 for (camp::idx_t i = 0; i < n; ++i)
879 for (camp::idx_t i = 0; i < n; ++i)
881 q.
set(this->
get(i) / b, i);
896 if (s_num_full_registers == 0)
898 return m_registers[0].min_n(s_num_partial_lanes);
902 for (camp::idx_t i = 1; i < s_num_full_registers; ++i)
904 result = RAJA::min<element_type>(result, m_registers[i].
min());
906 if (s_num_partial_lanes)
908 result = RAJA::min<element_type>(
909 result, m_registers[s_final_register].min_n(s_num_partial_lanes));
923 if (N < s_register_num_elem)
925 return m_registers[0].min_n(N);
929 for (camp::idx_t reg = 1; reg < s_num_full_registers; ++reg)
931 if (N >= reg * s_register_num_elem + s_register_num_elem)
933 result = RAJA::min<element_type>(result, m_registers[reg].
min());
937 return RAJA::min<element_type>(
938 result, m_registers[reg].min_n(N - reg * s_register_num_elem));
941 if (N - s_num_full_registers * s_register_num_elem > 0)
943 result = RAJA::min<element_type>(
944 result, m_registers[s_final_register].min_n(
945 N - s_final_register * s_register_num_elem));
960 if (s_num_full_registers == 0)
962 return m_registers[0].max_n(s_num_partial_lanes);
966 for (camp::idx_t i = 1; i < s_num_full_registers; ++i)
968 result = RAJA::max<element_type>(result, m_registers[i].
max());
970 if (s_num_partial_lanes)
972 result = RAJA::max<element_type>(
973 result, m_registers[s_final_register].max_n(s_num_partial_lanes));
987 if (N < s_register_num_elem)
989 return m_registers[0].max_n(N);
993 for (camp::idx_t reg = 1; reg < s_num_full_registers; ++reg)
995 if (N >= reg * s_register_num_elem + s_register_num_elem)
997 result = RAJA::max<element_type>(result, m_registers[reg].
max());
1001 return RAJA::max<element_type>(
1002 result, m_registers[reg].max_n(N - reg * s_register_num_elem));
1005 if (N - s_num_full_registers * s_register_num_elem > 0)
1007 result = RAJA::max<element_type>(
1008 result, m_registers[s_final_register].max_n(
1009 N - s_final_register * s_register_num_elem));
1024 for (camp::idx_t i = 1; i < s_num_registers; ++i)
1026 s += m_registers[i];
1049 for (camp::idx_t i = 0; i < s_num_registers; ++i)
1051 dp += m_registers[i].dot(
x.vec(i));
1061 m_registers[to_register(idx)].
set(val, to_lane(idx));
1070 return m_registers[to_register(idx)].get(to_lane(idx));
1081 std::string s =
"Vector(" + std::to_string(s_num_elem) +
")[ ";
1084 for (camp::idx_t i = 0; i < s_num_elem; ++i)
1086 s += std::to_string(this->
get(i)) +
" ";
1089 camp::idx_t physical_size = s_num_registers * s_register_num_elem;
1090 if (s_num_elem < physical_size)
1093 for (camp::idx_t i = s_num_elem; i < physical_size; ++i)
1095 s += std::to_string(this->
get(i)) +
" ";
RAJA header file defining a bit masking operator.
RAJA header file defining SIMD/SIMT register operations.
Header file containing RAJA simd policy definitions.
Definition: RegisterBase.hpp:39
Definition: VectorRegisterImpl.hpp:51
RAJA_INLINE RAJA_HOST_DEVICE element_type max_n(int N) const
Returns the largest element over the first N lanes.
Definition: VectorRegisterImpl.hpp:984
RAJA_INLINE RAJA_HOST_DEVICE TensorRegister(self_type const &c)
Definition: VectorRegisterImpl.hpp:128
RAJA_INLINE RAJA_HOST_DEVICE element_type max() const
Returns the largest element.
Definition: VectorRegisterImpl.hpp:957
RAJA_HOST_DEVICE RAJA_INLINE self_type & load_strided_n(element_type const *ptr, int stride, int N)
Definition: VectorRegisterImpl.hpp:562
RAJA_HOST_DEVICE RAJA_INLINE self_type const & store_strided(element_type *ptr, int stride) const
Definition: VectorRegisterImpl.hpp:684
self_type operator*(SquareMatrixRegister< T2, L, RP > const &y) const
Definition: VectorRegisterImpl.hpp:204
RAJA_INLINE RAJA_HOST_DEVICE TensorRegister(RHS const &rhs)
Definition: VectorRegisterImpl.hpp:139
RAJA_HOST_DEVICE RAJA_INLINE self_type const & store_strided_n(element_type *ptr, int stride, int N) const
Definition: VectorRegisterImpl.hpp:736
RAJA_INLINE RAJA_HOST_DEVICE self_type & gather(element_type const *ptr, int_vector_type offsets)
Generic gather operation for full vector.
Definition: VectorRegisterImpl.hpp:604
RAJA_HOST_DEVICE RAJA_INLINE element_type get(int idx) const
Definition: VectorRegisterImpl.hpp:1068
RAJA_HOST_DEVICE RAJA_INLINE TensorRegister(element_type c)
Definition: VectorRegisterImpl.hpp:123
RAJA_SUPPRESS_HD_WARN RAJA_HOST_DEVICE RAJA_INLINE self_type divide_n(self_type const &b, camp::idx_t n) const
Divide n elements of this vector by another vector.
Definition: VectorRegisterImpl.hpp:856
RAJA_HOST_DEVICE RAJA_INLINE element_type dot(self_type const &x) const
The dot product of two vectors.
Definition: VectorRegisterImpl.hpp:1046
RAJA_INLINE std::string to_string() const
Converts to vector to a string.
Definition: VectorRegisterImpl.hpp:1079
RAJA_HOST_DEVICE RAJA_INLINE self_type & load_packed(element_type const *ptr)
Definition: VectorRegisterImpl.hpp:485
RAJA_HOST_DEVICE RAJA_INLINE self_type const & store_packed_n(element_type *ptr, int N) const
Definition: VectorRegisterImpl.hpp:706
RAJA_HOST_DEVICE RAJA_INLINE self_type const & scatter_n(element_type *ptr, int_vector_type const &offsets, camp::idx_t N) const
Generic scatter operation for n-length subvector.
Definition: VectorRegisterImpl.hpp:801
RAJA_INLINE RAJA_HOST_DEVICE element_type min() const
Returns the largest element.
Definition: VectorRegisterImpl.hpp:893
typename register_type::int_vector_type::element_type int_element_type
Definition: VectorRegisterImpl.hpp:69
RAJA_HOST_DEVICE RAJA_INLINE TensorRegister(register_type reg0, REGS const &... regs)
Definition: VectorRegisterImpl.hpp:147
RAJA_HOST_DEVICE static constexpr RAJA_INLINE bool is_ref_packed()
Definition: VectorRegisterImpl.hpp:165
RAJA_HOST_DEVICE static constexpr RAJA_INLINE bool is_root()
Definition: VectorRegisterImpl.hpp:155
RAJA_INLINE RAJA_HOST_DEVICE element_type min_n(int N) const
Returns the smallest element over the first N lanes.
Definition: VectorRegisterImpl.hpp:920
RAJA_HOST_DEVICE RAJA_INLINE self_type & set(element_type val, int idx)
Definition: VectorRegisterImpl.hpp:1059
RAJA_HOST_DEVICE constexpr RAJA_INLINE TensorRegister()
Definition: VectorRegisterImpl.hpp:118
RAJA_HOST_DEVICE RAJA_INLINE self_type & operator=(self_type const &c)
Definition: VectorRegisterImpl.hpp:197
RAJA_HOST_DEVICE RAJA_INLINE self_type const & scatter(element_type *ptr, int_vector_type const &offsets) const
Generic scatter operation for full vector.
Definition: VectorRegisterImpl.hpp:774
RAJA_HOST_DEVICE RAJA_INLINE self_type divide(self_type const &den) const
Definition: VectorRegisterImpl.hpp:831
RAJA_HOST_DEVICE RAJA_INLINE self_type const & store_packed(element_type *ptr) const
Definition: VectorRegisterImpl.hpp:664
RAJA_HOST_DEVICE RAJA_INLINE self_type const & store_ref(REF_TYPE &ref) const
Definition: VectorRegisterImpl.hpp:221
RAJA_INLINE self_type & gather_n(element_type const *ptr, int_vector_type offsets, camp::idx_t N)
Generic gather operation for n-length subvector.
Definition: VectorRegisterImpl.hpp:628
RAJA_HOST_DEVICE static constexpr RAJA_INLINE camp::idx_t s_dim_elem(camp::idx_t dim)
Definition: VectorRegisterImpl.hpp:176
RAJA_INLINE RAJA_HOST_DEVICE element_type sum() const
Returns the sum of all elements.
Definition: VectorRegisterImpl.hpp:1020
RAJA_HOST_DEVICE RAJA_INLINE self_type & load_strided(element_type const *ptr, int stride)
Definition: VectorRegisterImpl.hpp:505
RAJA_HOST_DEVICE RAJA_INLINE self_type & operator=(element_type value)
Set entire vector to a single scalar value.
Definition: VectorRegisterImpl.hpp:188
camp::decay< T > element_type
Definition: VectorRegisterImpl.hpp:62
RAJA_HOST_DEVICE RAJA_INLINE self_type & load_packed_n(element_type const *ptr, int N)
Definition: VectorRegisterImpl.hpp:527
RAJA_HOST_DEVICE RAJA_INLINE self_type operator*(self_type const &x) const
The * operator of two vectors is a element-wise multiply.
Definition: VectorRegisterImpl.hpp:1038
RAJA_HOST_DEVICE RAJA_INLINE self_type & load_ref(REF_TYPE const &ref)
Definition: VectorRegisterImpl.hpp:214
RAJA_SUPPRESS_HD_WARN RAJA_HOST_DEVICE RAJA_INLINE self_type divide_n(element_type const &b, camp::idx_t n) const
Divide n elements of this vector by a scalar.
Definition: VectorRegisterImpl.hpp:876
Definition: TensorRegister.hpp:46
Definition: ExpressionTemplateBase.hpp:68
Definition: TensorRegisterBase.hpp:105
Header file for common RAJA internal macro definitions.
#define RAJA_HOST_DEVICE
Definition: macros.hpp:65
#define RAJA_SUPPRESS_HD_WARN
Definition: macros.hpp:68
TensorLayout< 0 > VectorLayout
Definition: TensorLayout.hpp:77
TensorTileSize
Definition: TensorRef.hpp:234
@ TENSOR_FULL
Definition: TensorRef.hpp:236
Definition: AlignedRangeIndexSetBuilders.cpp:35
RAJA_HOST_DEVICE constexpr RAJA_INLINE Result min(Args... args)
Definition: foldl.hpp:161
RAJA_HOST_DEVICE constexpr RAJA_INLINE RAJA::zip_tuple_element_t< I, zip_tuple< is_val, Ts... > > & get(zip_tuple< is_val, Ts... > &z) noexcept
Definition: zip_tuple.hpp:56
RAJA_HOST_DEVICE constexpr RAJA_INLINE Result max(Args... args)
Definition: foldl.hpp:155
RAJA header file defining SIMD/SIMT register operations.
Definition: BitMask.hpp:30
Definition: TensorLayout.hpp:35
RAJA_HOST_DEVICE static RAJA_INLINE void load_ref(self_type &self, RefType const &ref)
Performs load specified by TensorRef object.
Definition: VectorRegisterImpl.hpp:245
RAJA_HOST_DEVICE static RAJA_INLINE void store_ref(self_type const &self, RefType &ref)
Performs load specified by TensorRef object.
Definition: VectorRegisterImpl.hpp:298
RAJA::expt::TensorRegister< REGISTER_POLICY, T, RAJA::expt::VectorLayout, camp::idx_seq< SIZE > >::RefBridge< RAJA::internal::expt::StaticTensorRef< POINTER_TYPE, INDEX_TYPE, TENSOR_SIZE, camp::int_seq< INDEX_TYPE, STRIDE_VALUE >, camp::int_seq< INDEX_TYPE, BEGIN_VALUE >, camp::int_seq< INDEX_TYPE, SIZE_VALUE >, STRIDE_ONE_DIM > >::store_ref RAJA_HOST_DEVICE static RAJA_INLINE void store_ref(self_type const &self, RefType &ref)
Performs load specified by StaticTensorRef object.
Definition: VectorRegisterImpl.hpp:431
RAJA::expt::TensorRegister< REGISTER_POLICY, T, RAJA::expt::VectorLayout, camp::idx_seq< SIZE > >::RefBridge< RAJA::internal::expt::StaticTensorRef< POINTER_TYPE, INDEX_TYPE, TENSOR_SIZE, camp::int_seq< INDEX_TYPE, STRIDE_VALUE >, camp::int_seq< INDEX_TYPE, BEGIN_VALUE >, camp::int_seq< INDEX_TYPE, SIZE_VALUE >, STRIDE_ONE_DIM > >::load_ref RAJA_HOST_DEVICE static RAJA_INLINE void load_ref(self_type &self, RefType const &ref)
Performs load specified by StaticTensorRef object.
Definition: VectorRegisterImpl.hpp:378
Definition: TensorRef.hpp:472
Definition: TensorRef.hpp:426
index_type m_stride[NUM_DIMS]
Definition: TensorRef.hpp:442
pointer_type m_pointer
Definition: TensorRef.hpp:441
tile_type m_tile
Definition: TensorRef.hpp:443
index_type m_begin[NUM_DIMS]
Definition: TensorRef.hpp:246
index_type m_size[NUM_DIMS]
Definition: TensorRef.hpp:247